1. Field of the Invention
The present invention relates to a clock signal generator for television receivers, video tape recorders and the like, and more particularly to a clock signal generator used for generating a horizontal synchronizing signal for a composite video signal.
The present invention is based on Korean Application No. 95-34326 filed Oct. 6, 1995, which is incorporated herein by reference for all purposes.
2. Description of the Prior Art
Referring to FIG. 1 which illustrates a block diagram of a first prior art clock generator, the reference numeral 1 designates a video signal input terminal. A burst lock clock generator 4 receives an input from terminal 1 and provides a burst lock clock signal to a burst lock clock signal line 5. The burst lock clock signal is generated in synchronism with a color burst signal contained in a composite video signal applied to terminal 1. A synchronizing signal generator 9 produces a horizontal synch signal, synchronized with the burst lock clock signal, on a synchronizing signal output terminal 1. A signal processor 10, which receives the burst lock clock signal on line 5 and the video signal on terminal 1 produces a video output signal on a video signal output terminal 12.
Referring to FIG. 2 which illustrates a block diagram of a second prior art clock generator, like numerals correspond to previously identified structure. A line lock clock generator 2 receives an input from terminal 1 and provides a line lock clock signal to a line lock clock signal line 3. The line lock clock signal is generated in synchronism with a horizontal synchronizing signal contained in the composite video signal applied to terminal 1. Synchronizing signal generator 9 produces a horizontal synch signal, synchronized with the line lock clock signal, on terminal 11. Signal processor 10, which receives the line lock clock signal on line 3 and the video signal on terminal 1, produces a video output signal on a video signal output terminal 12.
Referring to FIG. 1, the burst lock clock generator 4 generates a stable burst lock clock signal on line 5 by using a crystal oscillator (not shown). The burst lock clock signal 5 is synchronized with the color burst signal contained in the input video signal supplied through video signal input terminal 1. The input video signal is a signal which is in accordance with a standard television broadcasting system (hereinafter referred to as a "standard signal"). In an NTSC system, the relation between the frequency f.sub.sc of the color burst signal contained in the standard signal and the frequency f.sub.H of the horizontal synchronizing signal can be expressed in the following equation: EQU f.sub.sc =(455/2)f.sub.H
Non-NTSC input video signals which do not satisfy the above equation are called "non-standard signals."
The synchronizing signal generator 9 receives the burst lock clock signal on line 5 supplied from the burst lock clock generator 4 and generates a horizontal synch signal using the relation expressed by the above equation.
The signal processor 10 receives both the input video signal supplied through the video signal input terminal I and the burst lock clock signal on line 5. Signal processor 10 processes the video signal by using the relation expressed by the above equation to thereby improve the image quality of the video signal. An example of such a conventional circuit for improving the image quality of the video signal is disclosed in Japanese Patent Laid-open Gazette No. 62-268274 which is incorporated by reference.
Referring now to FIG. 2, the line lock clock generator 2 generates the line lock clock signal on line 3. The signal on line 3 is synchronized with a horizontal synchronizing signal contained in an input video signal and supplied through the video signal input terminal 1.
The synchronizing signal generator 9 receives the line lock clock signal 3, supplied from the line lock clock generator 2, and generates a horizontal synch signal therefrom.
The signal processor 10 receives both the video signal supplied through the video signal input terminal 1 and the line lock clock signal on line 3 supplied from the line lock clock generator 2, and performs signal processing on the input video signal. An example of such a conventional circuit as shown in FIG. 2 is disclosed in Japanese Patent Laid-open Gazette No. 63-193783 which is incorporated by reference.
The clock generator of FIG. 1, using a burst lock method, enables one to generate a very stable synchronizing signal. More importantly, however, the image quality of a standard input video signal can be improved. However, when the input video signal is a non-standard signal, such as a video signal reproduced by a video tape recorder, it is impossible to improve the image quality because the input video signal is not accurately synchronized with the synchronizing clock signal.
The clock pulse generator of FIG. 2, using a line lock method, has an advantage in that even a non-standard input video signal can be synchronized with a clock signal to a sufficient level to improve image quality. By detecting a horizontal synchronizing signal in the input video signal, a clock signal which is synchronized with the input video signal can be generated. However, if a standard signal which does not satisfy the relation expressed by the above equation is supplied, the image quality can not be improved to a sufficient level, because accuracy of synchronization between the input video signal and the clock signal in FIG. 2 is lower than that in FIG. 1.
FIG. 3 illustrates a block diagram showing a conventional line-lock/burst-lock clock generator as disclosed in U.S. Pat. No. 5,025,310 which is incorporated herein by reference.
Referring to FIG. 3, previously used numerals identify like structure. Included therein are a video signal input terminal 1, a line lock clock generator 2, a line lock clock signal 3, a burst lock clock generator 4, a burst lock clock signal 5, a standard/non-standard signal detector 6, a phase comparator 7&, switches 8a, 8b, a synchronizing signal generator 9, a signal processor 10, a synchronizing signal output terminal 11, a video signal output terminal 12, an adder 17, a synchronizing signal separator/phase comparator 18, and a voltage-controlled oscillator 19.
A video signal is supplied through the video signal input terminal 1, to the line lock clock generator 2, to the burst lock clock generator 4, and to the standard/non-standard signal detector 6. The line lock clock generator 2 separates a horizontal synchronizing signal contained in the video signal, and generates the line lock clock signal 3 having a frequency 1820 times that of the frequency f.sub.H of the horizontal synchronizing signal. This is accomplished by using a phase-locked loop (PLL) circuit which includes the adder 17, the synchronizing signal separator/phase comparator 18, and the voltage-controlled oscillator 19.
The burst lock clock generator 4 separates a color burst signal contained in the video signal, and generates the burst lock clock signal on line 5 having a frequency of 8 times as high as the frequency f.sub.sc of the color burst signal. This is accomplished by using a crystal oscillator (not shown) which is provided in the burst lock clock generator 4. Since the burst lock clock signal 5 is generated by the crystal oscillator as described above, the burst lock clock signal 5 is very stable.
The synchronizing signal generator 9 receives the line lock clock signal 3, and generates a horizontal synchronizing signal of the input video signal by lowering the frequency of the line lock clock signal on line 3. This horizontal synchronizing signal is then applied to synchronizing signal output terminal 11.
The standard/non-standard signal detector 6 determines whether or not the frequency f.sub.H of the horizontal synchronizing signal of the input video signal and the frequency f.sub.sc of the color burst signal satisfy the relation expressed by the above equation. When the relation expressed by the above equation is satisfied, the standard/non-standard signal detector 6 determines that the input video signal is a standard signal. When the relation expressed by the above equation is not satisfied, the standard/non-standard signal detector 6 determines that the input video signal is a non-standard signal.
The switch 8a receives a detection signal supplied from the standard/non-standard signal detector 6. When the input video signal is a non-standard signal, the switch 8a is turned or closed to the line lock clock (L) side, as shown by the dotted line in FIG. 3. Alternately, when the input video signal is a standard signal, the switch 8a is turned or closed to the burst lock clock (B) side, as shown by the solid line in FIG. 3. Accordingly, either one of the line lock clock signal or the burst lock clock signal is supplied to the signal processor 10. The signal processor 10 receives the video signal from the video signal input terminal 1, and performs digital signal processing by using the clock signal supplied through the switch 8a to improve image quality. The processed video signal is then transmitted through the video signal output terminal 12.
The phase comparator 7 receives and compares the line lock clock signal 3 and the burst lock clock signal 5. The comparator 7 then supplies a signal to switch 8b corresponding to the phase difference between the line lock clock signal 3 and the burst lock clock signal 5. As with switch 8a, the operation of the interlocked switch 8b is controlled based on the detection signal generated by the standard/non-standard signal detector 6. When the input video signal is a standard signal, the switch 8b is turned to the C side so as to be closed as shown by a solid line. Alternately, when the input video signal is a nonstandard signal, the switch 8b is turned to the O side so as to be opened as shown by a dotted line. Accordingly, the switch 8b serves to supply the output signal of the phase comparator 7 to the line lock clock generator 2 only when the input video signal is a standard signal.
The line lock/burst lock clock generator constructed as mentioned above 00 eliminates the disadvantages of the circuits shown in FIGS. 1 and 2, in which a line lock method and a burst lock method are adopted, individually. However, the line lock/burst lock clock generator of FIG. 3 still has a disadvantage in that noise is generated when the input video signal changes from a standard signal to a non-standard signal or from a non-standard signal to a standard signal. That is, noise results when the line lock clock signal and the burst lock clock signal are switched by the switch 8a. Furthermore, construction of the generator shown in FIG. 3 is complicated due to addition of the standard/non-standard signal detector and switches.